NVDA

NVDA — Nvidia

TL;DR

Nvidia sits at the center of the AI buildout and is extending, not defending. GTC 2026 showed a platform that has absorbed Groq (via a $20B licensing “acquihire”), put co-packaged optics on the Rubin Ultra and Feynman roadmaps, and formalized disaggregated inference as Nvidia doctrine with LPX + Attention-FFN Disaggregation.¹² Near-term, Nvidia is supply-constrained by TSMC N3 and HBM4; the moat is widening into memory tiers (CMX/STX), storage, and networking silicon rather than narrowing.³¹

Business

Designs and sells AI accelerators (Hopper, Blackwell, Blackwell Ultra, Rubin, Rubin Ultra, Feynman roadmap), gaming GPUs, and an increasingly integrated systems stack: NVLink switches, Spectrum-X Ethernet, BlueField DPUs, CX NICs, reference rack designs (Oberon, Kyber, LPX, Vera ETL256, STX), and software (CUDA + acquired Groq IP). Fabbed at TSMC (4NP → N3P for Rubin), packaged with CoWoS, paired with HBM from SK Hynix/Samsung/Micron.¹³ Automotive is a hidden $5–10B business spanning three computers: frontier training clusters (largest revenue driver, reported inside Data Center), Omniverse simulation nodes, and in-car SoCs (Orin/Thor) — the only line item reported as Automotive.⁴

Thesis

• Inference kingdom expansion. Nvidia “acquired” Groq for $20B in a licensing structure that avoided antitrust review, is productizing LP30/LP35 on Samsung SF4 (non-TSMC/HBM capacity = incremental supply nobody else can access), and will tape out LP40 on TSMC N3P for Feynman. LPU handles FFN; GPU handles attention (AFD). This extends the platform to low-latency decode scenarios where a pure-GPU setup was inefficient.¹
• CPO / scale-up optics roadmap. Rubin Ultra NVL576 (8× Oberon racks, inter-rack CPO, intra-rack copper) introduces CPO at low volume for test. Feynman NVL1152 is the volume CPO ramp. Copper remains within-rack through Rubin Ultra; NVL72/NVL144 Kyber are all-copper.¹⁵
• Vera CPU + 3× host DRAM content. VR NVL72 carries 1,536 GB DDR per Vera vs. 512 GB per Grace — a 3× step-up that drags server DRAM demand with every rack. Vera ETL256 (256 CPUs/rack, liquid-cooled, all-copper) addresses the RL/agentic workload CPU bottleneck.¹³
• Storage/memory tier capture (CMX + STX). BlueField-4 based storage platform standardizes KV-cache offload (“tier G3.5”) and the STX reference rack locks ~16 storage vendors (Dell, HPE, NetApp, VAST, Cloudian, Pure’s mention was absent but QCT and Supermicro were named) onto Nvidia’s network + DPU stack. Nvidia is moving up the infra stack beyond compute and network.¹
• Supply-constrained, not demand-constrained. AI takes ~60% of 2026 N3 output (model); 2027 is 86%. TSMC “kingmaker” is prioritizing AI over smartphone allocation; any smartphone weakness releases more wafers straight to Rubin/TPU. Anthropic added $6B ARR in February 2026 alone on Claude Code — demand side shows no sign of easing.³
• Automotive three-computer TAM. Jensen put total automotive revenue at $5–10B(includingtraining+simulation);Hyundaialonesigneda50,000BlackwellGPUcontractworthanestimated$1.5–2.5B that flows into the Data Center line, not Automotive. Nvidia can lose the in-car socket to Qualcomm or Tesla and still capture training and Omniverse simulation dollars.⁴
• Neocloud distribution lock-in. Neoclouds in which Jensen is an investor (CoreWeave, Nebius, Crusoe, Together, Lambda, Firmus, Nscale) face strong incentives not to adopt TPUs, AMD GPUs, or even Arista switches. This effectively walls off a significant segment of the third-party hosting market from Google/AWS custom silicon.⁶

Risks

• Custom silicon displacement — TPU externalization. Google is now selling TPUv7 Ironwood systems to external customers: Anthropic is taking 400k Ironwoods direct (~$10B,soldbyBroadcom)plus600kthroughGCP($42B RPO). Meta, SSI, xAI, OpenAI are in line. Critically, OpenAI secured ~30% off its entire Nvidia GPU fleet just by threatening TPU adoption — before deploying a single TPU. SemiAnalysis still calls Nvidia “king of the jungle” but notes Jensen must accelerate or risk the same complacency fate as Intel in CPUs.⁶
• Custom silicon displacement — Trainium3. AWS Trainium3 (TSMC N3P, GA late 2025) targets perf per TCO head-on, adding a switched scale-up topology and doubling MXFP8 throughput. Trainium4 will include an NVLink 6 fusion track — Nvidia enabling interoperability at favorable pricing to protect system-level lock-in. Three concurrent fronts: TPUv7, AMD MI450X, Trainium3.⁷
• HBM4 pin-speed miss at Micron. Nvidia targets ~11 Gb/s on HBM4; SK Hynix and Samsung are progressing, Micron is lagging. Single-source risk if any one vendor struggles to yield.³
• CPO execution. Jensen’s “NVL1152 in Feynman is all CPO” was a Q&A remark, not a blog commitment — SemiAnalysis notes disagreement on whether copper survives within-rack into Feynman. Schedule slippage possible.¹
• Samsung foundry encroachment. Samsung has entered Nvidia’s datacenter supply chain (reportedly LP30/LP35 on SF4, plus rumored Tesla AI5/AI6 dual-sourcing). Good for supply; dilutes TSMC exclusivity.³
• Groq integration risk. LPU3 (LP30) is a non-Nvidia-designed chip with a fixed SerDes that had been failing; LP40 is the first deeply co-designed part and a year+ out. Execution slip is possible.¹

Recent catalysts

• 2026-04-15 — ISSCC 2026 papers: Nvidia + Broadcom detail CPO components.⁸
• 2026-02-17 — Chipstrat: Nvidia automotive business is $5–10Bacrossthreecomputers;singleHyundaiGPUcontractworth$1.5–2.5B flows into Data Center segment.⁴
• 2025-12-04 — AWS Trainium3 GA + Trainium4 announced at re:Invent; Trainium4 to include NVLink 6 fusion track.⁷
• 2025-11-28 — SemiAnalysis: Google externalize TPUv7; Anthropic signs 1M TPU deal (400k direct + 600k GCP). OpenAI extracts ~30% Nvidia discount by credibly threatening TPU switch.⁶
• 2026-03-31 — Dissecting Blackwell Tensor Core deep dive.⁹
• 2026-03-24 — GTC 2026 recap: LPX rack, Vera ETL256, STX, Feynman sneak peek, CPO roadmap.¹
• 2026-03-12 — Great AI Silicon Shortage: N3 is the binding constraint; AI is 60% of 2026 N3 output.³
• 2026-02-25 — Vera Rubin extreme co-design piece.¹⁰
• 2026-02-16 — InferenceX v2: Blackwell vs AMD vs Hopper benchmark.²
• 2026-01-01 — Co-packaged optics scaling book.⁵

Second-order reads

• 2026-04-14 — Edgewater Research, Memory/Storage (MU/SNDK) Update — NVDA forecasting 23–25B 1Gb DRAM demand CY26, potentially growing to 60–70B in CY27; securing SOCAMM2 supply aggressively. NVDA ICMS rack targeting ~30TB to achieve 3–5x read/write per day performance for ICM solution (one ICM rack supporting up to 8 NVL racks, ~12PBs total per rack). HBM demand from NVDA unchanged M/M in high-30B 1Gb-unit range; Hynix holds 60–70% share. → Memory supplier channel checks validate the Vera/Rubin DRAM footprint magnitude; NVDA remains the primary driver of DRAM supply tightness.¹¹
• 2026-04-13 — FundaAI, Preview: ASML 1Q26 — TSMC revising EUV procurement upward on advanced-node shortage; Anthropic ARR >$30B;4majorCSPs2026capexnowexpected$620B. Direct read: Nvidia supply-constrained through 2026 and into 2027, pricing power intact.¹²
• 2026-04-10 — FundaAI, Preview: TSMC 1Q26 — continued front-end demand. Positive for Nvidia wafer access improving into 2H26.¹³
• 2026-03-23 — Chipstrat, Multi-silicon era is here — disaggregation is “official Nvidia doctrine.” Validates the LPX/AFD thesis.¹⁴
• 2026-02-27 — Irrational Analysis on Groq integration dataflow — skeptical on standalone LPU economics but sees Nvidia integration as the only viable path.¹⁵
• 2025-11-27 — Citrini, Carving up the TPU — Anthropic + Meta adopting TPUs raises competitive questions for Nvidia on the highest-end.¹⁶

Valuation & positioning

Pending. No specific multiple target surfaced in the corpus yet — gather from FundaAI / Irrational Analysis earnings previews as they land.

Sources

Related

AMD AVGO MRVL — accelerator + networking competitive set TSM — foundry; N3 allocation is Nvidia’s binding constraint ASML — lithography pull-through from TSMC N3/N2 ramp MU SNDK — HBM supplier (MU lagging on HBM4 yield) ALAB CRDO — interconnect pull-through (PCIe/CXL + scale-up AECs) LITE COHR AAOI FN CIEN MTSI — optics pull-through on 1.6T + CPO DELL SMCI — AI systems downstream INTC — Intel Foundry as potential overflow capacity

Footnotes

1. SemiAnalysis — Nvidia: The Inference Kingdom Expands — 2026-03-24 ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶ ↩⁷ ↩⁸ ↩⁹ ↩¹⁰

2. SemiAnalysis — InferenceX v2: NVIDIA Blackwell vs AMD vs Hopper — 2026-02-16 ↩ ↩²

3. SemiAnalysis — The Great AI Silicon Shortage — 2026-03-12 ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶ ↩⁷

4. Chipstrat — The Nvidia Business Hiding in Plain Sight — 2026-02-17 ↩ ↩² ↩³

5. SemiAnalysis — Co-Packaged Optics (CPO) Book Scaling — 2026-01-01 ↩ ↩²

6. SemiAnalysis — TPUv7: Google Takes a Swing at the King — 2025-11-28 ↩ ↩² ↩³

7. SemiAnalysis — AWS Trainium3 Deep Dive: A Potential Challenger Approaching — 2025-12-04 ↩ ↩²

8. SemiAnalysis — ISSCC 2026: Nvidia and Broadcom CPO — 2026-04-15 ↩

9. SemiAnalysis — Dissecting Nvidia Blackwell Tensor — 2026-03-31 ↩

10. SemiAnalysis — Vera Rubin: Extreme Co-Design — 2026-02-25 ↩

11. SNDK) Update — 2026-04-14 ↩

12. FundaAI — Preview: ASML 1Q26 — 2026-04-13 ↩

13. FundaAI — Preview: TSMC 1Q26 — 2026-04-10 ↩

14. Chipstrat — The Multi-Silicon Era Is Here — 2026-03-23 ↩

15. Irrational Analysis — It’s the Dataflow (Groq) — 2026-02-27 ↩

16. Citrini Research — Carving Up the TPU — 2025-11-27 ↩